As an alternative to the conventional dual-loop architecture, referenceless clock data recovery (CDR) architectures have become more popular in industry because of their simplicity and flexibility. However, the robustness of the transition between frequency acquisition and phase locking is always a concern, particularly for the linear CDR, which has an extremely limited capture range.
Many works, based mainly on the Pottbacker frequency detector (FD) [1], have been reported. In Lee [2] the capture range of the FD was only ±2.4% at 20 Gb/s with no capacitor bank in the voltage control oscillator (VCO); in Anond [3] the capture range of the FD was about ±6.4% at 2.75 Gb/s, with an 8-bit resolution of the capacitor bank in the VCO; in Kocaman [4] the capture range was ±15% at 10 Gb/s, with an 11-bit resolution of the capacitor bank. Thus the Pottbacker FD inherently suffers from a limited capture range, requiring a dedicated FD and a stringent tradeoff between the CDR capture range and the number of VCO bands. In the presence of input jitter and phase detector nonidealities, it is difficult to design an architecture where the resolution of the capacitor bank and the turnoff mechanism can guarantee that the VCO frequency will eventually fall within the pull-in range of the CDR.
In view of the foregoing, it is therefore desirable to provide a circuit that recovers a full-rate clock signal from a random digital data signal that has a very wide acquisition range.